LayEd Pro : A Full Custom Layout Editor
CifGDS Pro : CIF/GDSII Translator
MyDRC Pro : A Design Rule Checker
LayNet Pro : SPICE Netlist Extractor & Electrical Rule Checker
MyLVS Pro : Layout & Schematic Netlist Comparator

* Main Feature

- Full Custom Layout, MEMS Layout, Photo MASK Layout, LCD Layout
- DRC LVS Verification, GDS DXF Conversion

SchEd_Analog : Schematic/Symbol Editor
Logic2SPICE : SPICE Netlist Extractor
Analog : Analog Library
MySPICE : Analog Circuit Simulator
MyGPP : Graphical Post Processor

SchEd_Logic : Schematic/Symbol Editor
MySim : Logic Simulator, Wave displayer
Logic2EDIF : EDIF Translator
Xilinx, Altera, SCMOS, Library

MyVHDL : VHDL Modeling and Analysis, Compiler & Simulator
Waveform Editor : Automatic Test-bench Generator

FPGA and ASIC prototype systems

MyCAD Introduction
A suite of MyCAD
MyCAD design flow
Major customer
MPW & SEMICONDUCTOR Introduction
MPW Solution
Foundry Solution
ASIC Introduction
ASIC Design Service
LowPower Design Service
IP Service
IoT Business IoT
COMPANY Introduction
Location
Support
Contact


303 Jangwon Blog., 139-1 Garak-ro, Songpa-gu, Seoul, 138-850, Korea
TEL : +82-2-3432-1210 FAX : +82-2-3432-8855

Copyright(C) Seloco, Inc. All rights reserved.